Course Information
From COE1502
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[edit] Course Description
The objective of this course is to teach the tools and techniques used in the design of large scale digital systems. The course consists of a series of design projects centered on modern microprocessor design. This design experience is intended to teach you both the context and content of the design process. As context, you will learn to use a set of design tools in a modern commercial design flow and about the dynamics of working in a design group. As content, you will explore the design of a moderm microprocessor, see the design tradeoffs within its implementation, and learn how to evaluate good (and bad) design choices.
[edit] Instructor
Professor Donald Chiarulli Email: don@cs.pitt.edu Office: 5427 SENSQ
[edit] Teaching Assistants
Sam Dickerson Email: sjdst31@pitt.edu Office: 224 Benedum Hall
Joe Jezak Email: jjezak@cs.pitt.edu AIM: josejx2 Office: 5426 SENSQ
[edit] Time/Location
Tuesdays and Thursdays 2:30PM to 4:20PM 367 Benedum Hall
[edit] Textbooks
Required Text:
Computer Organization and Design: The Hardware/Software Interface
David Patterson and John Hennessey
4th edition
Morgan Kaufmann Publishing
Recommended Text:
The Student's Guide to VHDL
Peter Ashenden
1st edition
Morgan Kaufmann Publishing
See MIPS Run, Second Edition
Dominic Sweetman
2nd edition
Morgan Kaufmann Publishing
The required text is the same as what is used for the undergraduate computer architecture course (COE/CS 1541). For the reccommended texts, any modern VHDL and MIPS references will be sufficient, the above is just what we reccommend.
[edit] Prerequisites
You must be currently enrolled in or have already completed COE/CS 1541: Introduction to Computer Architecture. This is a firm prerequisite and you cannot take the course without meeting this requirement.
[edit] Grading Policy
This is a design class. During the semester you will work on a series of designs that build on each other as components of a system design Your final grade will be determined based on each of the project grades that your group receives and your grade on a final/practical exam at the end of the semester. Consider the group partner policy below carefully as each project group will turn in only one design and all members will receive the same grade.
- Project 1 (10%): Introduction to the design tools and methods
- Project 2 (10%): State Machine Design/UART
- Project 3 (20%): Single issue pipelined CPU
- Project 4 (15%): System Bus Interface
- Project 5 (20%): Memory Controller and L1 cache memory
- Final Exam (25%)
[edit] Academic Integrity Statement
Cheating/plagiarism will not be tolerated. Students suspected of violating the University of Pittsburgh Policy on Academic Integrity, from the February 1974 Senate Committee on Tenure and Academic Freedom reported to the Senate Council, will be required to participate in the outlined adjudication process as initiated by the instructor. A minimum sanction of a zero score for the quiz or exam will be imposed. Academic dishonesty includes plagiarism of programs, solutions to homework problems, papers, reports, exams or any other materials turned in for course credit.